The mathematical and circuit analyses of the converter show that the output current of the dc - dc converter tends to be saturated with the gradually increasing product of the operation frequency and the capacitor capacitance in the case of a determinate effective loop resistance 分別用matlab和pspice從理論和電路兩個方面進行的仿真研究都表明:在等效同路電阻一定的情況下, dc - dc變換器的輸出電流隨工作頻率和電容容量乘積的增大而趨于飽和。